5-channel esd protection array PACDN009 ?2010 scillc. all rights reserved. publication order number: may 2010 rev. 3 PACDN009/d features ? five channels of esd protection ? 8kv contact, 15kv air esd protection per channel (iec 61000-4-2 standard) ? 15kv of esd protection per channel (hbm) ? low loading capacitance (3pf typical) ? low leakage current is ideal for battery-powered devices ? available in miniature 8-lead msop package ? rohs compliant (lead-free) finishing applications ? consumer electronic products ? cellular phones ? pdas ? notebook computers ? desktop pcs ? digital cameras and camcorders ? vga (video) port protection for desktop and portable pcs product description the PACDN009 is a diode array designed to provide 5 channels of esd protection for electronic components or sub-systems. each channel consists of a pair of diodes which steers an esd current pulse to either the positive (v p ) or negative (v n ) supply. the PACDN009 protects against esd pulses up to 15kv human body model (100 pf capacitor discharging through a 1.5k resistor), and 8kv contact discharge, per international standard iec 61000-4-2. this device is particularly well-suited for portable electronics (e.g., cellular phones, pdas, notebook computers) because of its small package footprint, high esd protection level, and low loading capacitance. it is also suitable for protecting video output lines and i/o ports in computers and peripherals and is ideal for a wide range of consumer electronics products. the PACDN009 is supplied in an 8-lead msop pack- age and is available with rohs compliant lead-free finishing.
PACDN009 rev. 3 | page 2 of 10 | www.onsemi.com electrical schematic typical application circuit PACDN009 i/o port buffers connector expansion handheld/pd a esd protection 14 56 8 7 3 0.22 f* * capacitor should be placed as close as possib le to pin7 package / pinout diagrams PACDN009 1 2 3 4 8 7 6 5 ch 1 n.c. v n ch 2 ch 5 v p ch 4 ch 3 top view note: this drawing is not to scale. 8-lead msop package 0 0 9 r
PACDN009 rev. 3 | page 3 of 10 | www.onsemi.com pin descriptions pin name type description 1 ch 1 i/o esd channel 2 n.c. - no connect 3 v n gnd negative voltage supply rail or ground reference rail 4 ch 2 i/o esd channel 5 ch 3 i/o esd channel 6 ch 4 i/o esd channel 7 v p supply positive voltage supply rail 8 ch 5 i/o esd channel ordering information part numbering information lead-free finish leads package ordering part number 1 part marking 8 msop PACDN009mr 009r note 1: parts are shipped in tape & reel form unless otherwise specified.
PACDN009 rev. 3 | page 4 of 10 | www.onsemi.com specifications absolute maximum ratings parameter rating units supply voltage (v p - v n ) 6.0 v diode forward dc current (note 1) 20 ma operating temperature range -40 to +85 c storage temperature range -65 to +150 c dc voltage at any channel input (v n - 0.5) to (v p + 0.5) v package power rating 200 mw note 1: only one diode conducting at a time. standard operating conditions parameter rating units operating temperature range -40 to +85 c operating supply voltage (vp - vn) 0 to 5.5 v electrical operating characteristics (see note 1) symbol parameter conditions min typ max units ip supply current (vp-vn)=5.5v 10 a vf diode forward voltage if = 20ma 0.65 0.95 v vesd esd protection peak discharge voltage at any channel input, in system a) human body model, mil-std-883, method 3015 b) contact discharge per iec 61000-4-2 c) air discharge per iec 61000-4-2 note 2 notes 3 note 4 note 4 15 8 15 kv kv kv vcl channel clamp voltage positive transients negative transients @15kv esd hbm vp + 13.0 vn - 13.0 v v ileak channel leakage current 0 .1 1.0 a cin channel input capacitanc e @ 1 mhz, vp=5v, vn=0v, vin=2.5v; note 2 applies 3 5 pf note 1: all parameters specified at t a =25c unless otherwise noted. v p = 5v, v n = 0v unless noted. note 2: from i/o pins to v p or v n only. v p bypassed to v n with a 0.22 f ceramic capacitor (see application information for more details). note 3: human body model per mil-std-883, method 3015, c discharge = 100pf, r discharge = 1.5k , v p = 5.0v, v n grounded. note 4: standard iec 61000-4-2 with c discharge = 150pf, r discharge = 330w, v p = 5.0v, v n grounded.
PACDN009 rev. 3 | page 5 of 10 | www.onsemi.com performance information input capacitance vs. input voltage
PACDN009 rev. 3 | page 6 of 10 | www.onsemi.com application information design considerations in order to realize the maximum protection against esd pulses, care must be taken in the pcb layout to minimize parasitic series inductances on the suppl y/ground rails as well as the signal trace segment between the signal input (typically a connec tor) and the esd protection device. refer to figure 1 , which illustrates an example of a positive esd pulse striking an input channel. the parasitic series inductance back to the power supply is represented by l 1 and l 2 . the voltage v cl on the line being protected is: v cl = fwd voltage drop of d 1 + v supply + l 1 x d(i esd ) / dt+ l 2 x d(i esd ) / dt where i esd is the esd current pulse, and v supply is the positive supply voltage. an esd current pulse can rise from zero to its peak value in a very short time. as an example, a level 4 contact discharge per the iec61000-4- 2 standard results in a current pulse that rises from zero to 30 amps in 1ns. here d(i esd )/dt can be approximated by i esd / t, or 30/(1x10 -9 ). so just 10nh of series inductance (l 1 and l 2 combined) will lead to a 300v increment in v cl ! similarly for negative esd pulses, para sitic series inductance from the v n pin to the ground rail will lead to drastically increased negative voltage on the line being protected. another consideration is the output im pedance of the power supply for fa st transient currents. most power supplies exhibit a much higher output impedance to fast transient current spikes. in the v cl equation above, the v supply term, in reality, is given by (v dc + i esd x r out ), where v dc and r out are the nominal supply dc output voltage and effective out put impedance of the power supply respectively. as an example, a r out of 1 ohm would result in a 10v increment in v cl for a peak i esd of 10a. if the inductances and resistance described above are cl ose to zero, the rail-clamp esd protection diodes will do a good job of protecti on. however, since this is not possib le in practical situations, a bypass capacitor must be used to absorb the very high fr equency esd energy. so for any brand of rail-clamp esd protection diodes, a bypass capacito r should be connected between the v p pin of the diodes and the ground plane (v n pin of the diodes) as shown in the applicat ion circuit diagram below. a value of 0.22f is adequate for iec-61000-4-2 leve l 4 contact discharge protection ( + 8kv). ceramic chip capacitors mounted with short printed circuit board traces ar e good choices for this application. electrolytic capacitors should be avoided as they have poor high frequency characteristics. for extra protection, connect a zener diode in parallel with the bypass capac itor to mitigate the effects of the parasitic series inductance inherent in the capacitor. the breakdown voltage of the zener diode should be slightly higher than the maximum supply voltage. as a general rule, the esd protection array should be lo cated as close as possible to the point of entry of expected electrostatic discharges. the power supply bypass capacitor mentioned above should be as close to the v p pin of the protection array as possible, with minimum pcb trace lengths to the power supply, ground planes and between the signal input and the esd device to minimize stray series inductance. additional information see also california micro devices application note s ap209, ?design considerations for esd protection? and ap219, "esd protection for usb 2.0 systems"
PACDN009 rev. 3 | page 7 of 10 | www.onsemi.com figure 1. application of positive esd pulse between input channel and ground
PACDN009 rev. 3 | page 8 of 10 | www.onsemi.com figure 3. pcb layout recomendation
PACDN009 rev. 3 | page 9 of 10 | www.onsemi.com mechanical details msop-8 mechanical specifications, 8 pin the PACDN009 is supplied in a 8-pin msop package. dimensions are presented below. for complete information on the msop-8, see the ca lifornia micro devices msop package information document. package dimensions package msop pins 8 dimensions millimeters inches min max min max a 0.75 0.95 0.030 0.037 a1 0.05 0.15 0.002 0.006 b 0.28 0.38 0.011 0.015 c 0.13 0.23 0.005 0.009 d 2.90 3.10 0.114 0.122 e 2.90 3.10 0.114 0.122 e 0.65 bsc 0.026 bsc h 4.90 bsc 0.193 bsc l 0.40 0.70 0.016 0.028 # per tape and reel 4000 pieces controlling dimension: millimeters dimensions for msop-8 package
PACDN009 rev. 3 | page 10 of 10 | www.onsemi.com on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes witho ut further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any pr oduct or circuit, and specific ally disclaims any and all liability, including without li mitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or spec ifications can and do vary in different applications and actu al performance may vary over time. all operating parameters, including ?typicals? must be validated for each custom er application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not de signed, intended, or authorized for use as components in systems intended for surg ical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reason able attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : orderlit@onsemi.com n. american technical support : 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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